A method for generating weighted random test pattern
IBM Journal of Research and Development
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A testability metric for path delay faults and its application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan Encoded Test Pattern Generation for BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
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This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit.