SPADES: a simulator for path delay faults in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A non-enumerative path delay fault simulator for sequential circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-aware power noise reduction in layout
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |