Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A weighted random pattern test generation system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A testability metric for path delay faults and its application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Improving the proportion of at-speed tests in scan BIST
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Modeling Fault Coverage of Random Test Patterns
Journal of Electronic Testing: Theory and Applications
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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