Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
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A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.