Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
Improving the proportion of at-speed tests in scan BIST
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Low hardware overhead scan based 3-weight weighted random BIST
Proceedings of the IEEE International Test Conference 2001
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
At-Speed Logic BIST Architecture for Multi-Clock Designs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Logic BISTWith Scan Chain Segmentation
ITC '04 Proceedings of the International Test Conference on International Test Conference
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture
ATS '06 Proceedings of the 15th Asian Test Symposium
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of built-in test generator circuits using width compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On improving test quality of scan-based BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving test effectiveness of scan-based BIST by scan chain partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scanbased BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.