At-Speed Logic BIST Architecture for Multi-Clock Designs

Authors:
Laung-Terng Wang;Xiaoqing Wen;Po-Ching Hsu;Shianling Wu;Jonhson Guo
Affiliations:
SynTest Technologies, Inc.;Kyushu Institute of Technology, Japan;SynTest Technologies, Inc., Taiwan;SynTest Technologies, Inc.;SynTest Technologies, Inc., China
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

Citing 3
Cited 3

Logic BIST for Large Industrial Designs: Real Issues and Case Studies

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing of Digital Systems

Testing of Digital Systems
At-Speed Logic BIST for IP Cores

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.