A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Test Mode Selection & Insertion for RTL-BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Multiple Weight Set Calculation Algorithm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Effort-Minimized Logic BIST Implementation Method
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Encoded Test Pattern Generation for BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Impact of Test Point Insertion on Silicon Area and Timing during Layout
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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