Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper presents LBIST (Logic Built-In Self Test)design practice at Cisco Systems. It focuses on the LBISTdesign tasks that could affect design schedules and efforts.These are design timing closure and signature mismatchdebugging. Our timing closure technique guarantees timingclosure for LBIST insertion without any iterationbetween synthesis and LBIST insertion. In addition, itguarantees that only one iteration between static timinganalysis and LBIST insertion is required to close all timingviolations. The signature mismatch debugging techniqueeffectively identifies the causes by indicating the pattern,the scan flip-flop and its operation mode, where the mismatchhappens. These techniques save design efforts andthe product-to-market time. We have integrated thismethod into an ASIC design flow. The results of using thisflow in a large tele-communication design are described.