Low Overhead Test Point Insertion For Scan-Based BIST

Authors:
Michinobu Nakao;Seiji Kobayashi;Kazumi Hatayama;Kazuhiko Iijima;Seiji Terada
Affiliations:
-;-;-;-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 5
Cited 9

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Abstract

This paper presents a practical test pointinsertion method for scan-based BIST. To applytest point insertion in actual LSIs, especially highperformance LSIs, it is important to reduce thedelay penalty and the area overhead of the insertedtest points. Here efficient test point selectionalgorithms, which are suitable for utilizingoverhead reduction approaches such as restrictedcell replacement, test point flip-flops sharing, areproposed to meet the above requirements. Theeffectiveness of the algorithms is demonstrated bysome experiments.