Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Economics of Built-in Self-Test
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
GLFSR - A New Test Pattern Generator for Built-In Self-Test
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Chip Weighted Random Patterns
ATS '97 Proceedings of the 6th Asian Test Symposium
An Examination of PRPG Selection Approaches for Large, Industrial Designs
ATS '98 Proceedings of the 7th Asian Test Symposium
A Ring Architecture Strategy for BIST Test Pattern Generation
ATS '98 Proceedings of the 7th Asian Test Symposium
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Pseudo Random Patterns Using Markov Sources for Scan BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by conventionally selected seeds for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.