A course in number theory and cryptography
A course in number theory and cryptography
A method for generating weighted random test pattern
IBM Journal of Research and Development
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Arithmetic Pattern Generators for Built-In Self-Test
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are not properly adapted. This paper presents two different methods to minimize the test length without sacrificing fault coverage. The simulation-based reseeding method is suited to random pattern testable circuits and uses forward and reverse order simulation to skip ineffective patterns. The analytical method is appropriate for circuits with "hard" faults that are detected only by few test patterns. This method searches for an optimal input value of the accumulator and calculates the best seed analytically. The results show significant test length reductions. The proposed pattern generators can be implemented very efficiently in hardware using available blocks of a data path or in software using an embedded processor.