A method for generating weighted random test pattern
IBM Journal of Research and Development
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Arithmetic Pattern Generators for Built-In Self-Test
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Cellular automata for deterministic sequential test pattern generation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Multiple test set generation method for LFSR-based BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A New Built-in TPG Based on Berlekamp---Massey Algorithm
Journal of Electronic Testing: Theory and Applications
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The term "functional BIST" describes a test method tocontrol functional modules so that they generate a deterministictest set, which targets structural faults withinother parts of the system. It is a promising solution forself-testing complex digital systems at reduced costs interms of area overhead and performance degradation.While previous work mainly investigated the use of functional modules for generating pseudo-random andpseudo-exhaustive test patterns, the present paper shows that a variety of modules can also be used as adeterministic test pattern generator via an appropriatereseeding strategy. This method enables a BIST techniquethat does not introduce additional hardware like testpoints and test registers into combinational and pipelinedmodules under test. The experimental results prove thatthe reseeding method works for accumulator basedstructures, multipliers, or encryption modules as efficiently as for the classic linear feedback shift registers,and some times even better.