Principles of artificial intelligence
Principles of artificial intelligence
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation
IEEE Transactions on Computers
Load Balancing in a Hybrid ATPG Environment
IEEE Transactions on Computers
A probabilistic testability measure for delay faults
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers
Switch level random pattern testability analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Confidence analysis for defect-level estimation of VLSI random testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
On fault modeling for dynamic MOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
The Reliability of Approximate Testability Measures
IEEE Design & Test
A testability measure for hierarchical design environments
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Peak Power Reduction in Low Power BIST
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Random Pattern Fault Simulation in Multi-Valued Circuits
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Testability analysis of hierarchical finite state machines
EURO-DAC '91 Proceedings of the conference on European design automation
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault detection effectiveness of weighted random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A probabilistic analysis of coverage methods
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The CAD-tool PROTEST (Probabilistic Testability Analysis) is presented. PROTEST estimates for each fault of a combinational circuit its detection probability which can be used as a testability measure. Moreover it calculates the number of random test patterns which must be generated in order to achieve the required fault coverage.It is also demonstrated that the fault coverage will increase and the necessary number of random patterns will drastically decrease, if each primary input is stimulated by test patterns having specific probabilities of being logical “1”. PROTEST uses this fact and determines for each input the optimal signal probability for a randomly generated pattern.