PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Detecting resistive shorts for CMOS domino circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Static nMOS and static CMOS circuits show some serious problems for fault modeling and testing. In this paper we point out, that most of these problems are avoided by using dynamic nMOS or dynamic CMOS circuits. Stuck-open faults in this case do not result in sequential behaviour. A logical fault model is presented, where a fault of a logic gate will cause either a faulty combinational function or a degradation of the performance.Integrated test tools for technology dependent logical fault models based on random self test techniques are presented.