PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
“IBM perspectives on the electrical design automation industry” (keynote address)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Self-testing with correlated faults
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On fault modeling for dynamic MOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Generation of deterministic test patterns by minimal basic test sets
EURO-DAC '92 Proceedings of the conference on European design automation
Test pattern generation hardware motivated by pseudo-exhaustive test techniques
EURO-DAC '94 Proceedings of the conference on European design automation
A Gauss-elimination based PRPG for combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault detection effectiveness of weighted random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 0.00 |
Self testing of integrated circuits by random patterns has several technical and economical advantages. But there exists a large number of circuits which cannot be randomly tested, since the fault coverage achieved that way would be too low. In this paper we show that this problem can be solved by unequiprobable random patterns, and an efficient procedure is presented computing the specific optimal probability for each primary input of a combinational network.Those optimized random patterns can be produced on the chip during self test or off the chip in order to accelerate fault simulation and test pattern generation.