IEEE Transactions on Computers
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
On fault modeling for dynamic MOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Maximization of power dissipation under random excitation for burn-in testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
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The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and the test application can be done by a self-test technique or externally using linear feedback shift-registers. Unfortunately not all circuits are random-testable, since the fault coverage would be too low or the necessary test length would be too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. But there are also some circuits where no single optimal weight exists. In this paper it is shown that the problem is solved using several distributions instead of a single one. Furthermore an efficient procedure is presented computing the optimized input probabilities. Thisway all combinational circuits can be made random-testable. Fault simulation with weighted patterns shows a complete coverage of all non-redundant faults. The patterns can be successively produced by an external chip, and an optimized test scheme for circuits in a scan design can be established. As a result of its own formulas are derived determining sharp bounds of the probability that all faults are detected.