Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Reliability, Yield, and Stress Burn-in: A Unified Approach for Microelectronics Systems Manufacturing and Software Development
On Chip Weighted Random Patterns
ATS '97 Proceedings of the 6th Asian Test Symposium
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work proposes an approach to generate weightedrandom patterns which can maximally excite a circuitduring its burn-in testing. The approach is based on aprobability model and a maximization procedure to obtainsignal transition probability distribution for primary inputsand to generate weighted random patterns according to theobtained probability distribution. It can especially generateweighted random patterns to excite particularly selected"weak nodes" of the circuit in order to expose the earlyfailure of these nodes. Experimental results show that thisapproach can increase the power dissipation of the totalcircuit nodes up to 26.68% and the switching activity ofparticularly selected nodes up to 41.51% respectively.