Maximum current estimation in CMOS circuits

Surveys in combinatorics, 1993

Surveys in combinatorics, 1993

Resolving signal correlations for estimating maximum currents in CMOS combinational circuits

DAC '93 Proceedings of the 30th international Design Automation Conference

Gate-level timing verification using waveform narrowing

EURO-DAC '94 Proceedings of the conference on European design automation

Power distribution topology design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Estimation of maximum current envelope for power bus analysis and design

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Maximum power estimation using the limiting distributions of extreme order statistics

DAC '98 Proceedings of the 35th annual Design Automation Conference

Emerging power management tools for processor design

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Current signature compression for IR-drop analysis

Proceedings of the 37th Annual Design Automation Conference

Maximum current estimation considering power gating

Proceedings of the 2001 international symposium on Physical design

An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Proceedings of the 2002 international symposium on Physical design

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings of the 39th annual Design Automation Conference

Maximization of power dissipation under random excitation for burn-in testing

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

EDTC '97 Proceedings of the 1997 European conference on Design and Test

Maximum power estimation for CMOS circuits using deterministic and statistic approaches

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Maximum circuit activity estimation using pseudo-boolean satisfiability

Proceedings of the conference on Design, automation and test in Europe

Synthesis and implementation of active mode power gating circuits

Proceedings of the 47th Design Automation Conference

Maximum power estimation for CMOS circuits using deterministic and statistical approaches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems