Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Computing the maximum power cycles of a sequential circuit
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Maximum power estimation using the limiting distributions of extreme order statistics
DAC '98 Proceedings of the 35th annual Design Automation Conference
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Vector extraction for average total power estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power estimation starategies for a low-power security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wake-up protocols for controlling current surges in MTCMOS-based technology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
RT-level vector selection for realistic peak power simulation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
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Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs (PI's), it is CPU time intensive to conduct exhaustive search in the input vector space. The only feasible way is to find good upper and lower bounds of the maximum power, and to make the gap between these two bounds as narrow as possible. In this paper, we present a continuous optimization approach to efficiently generate tight lower bounds of the maximum instantaneous power for CMOS circuits. In our approach, each primary input (PI) of the circuit is allowed to assume any real number between 0 and 1. Maximum power estimation for CMOS circuits is then transformed into a continuous optimization problem, in which a smooth function is maximized over a unit hypercube in the Euclidean space. The continuous problem can be solved efficiently to generate good lower bounds of the maximum power. Our experiments with ISCAS and MCNC benchmark circuits demonstrate the superiority of this approach. For all the circuits tested, the mean value of the ratio "CPU time of the continuous optimization approach divided by CPU time of the simulation-based technique" is equal to 0.41. For 60% of the circuits tested, our approach gives a better estimate (1.16 times larger, on an average) than the simulation-based technique does. Compared to the ATPG-based technique, the continuous optimization approach generates a tighter lower bound (1.19 times larger, on an average) of maximum power for 60% of all the circuits tested.