Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Estimation of maximum power for sequential circuits considering spurious transitions
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Advanced Formal Verification
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for maximum satisfiability using unsatisfiable cores
Proceedings of the conference on Design, automation and test in Europe
Generating Worst-Case Stimuli for Accurate Power Grid Analysis
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Disproportionate instantaneous power dissipation may result in unexpected power supply voltage fluctuations and permanent circuit damage. Therefore, estimation of maximum instantaneous power is crucial for the reliability assessment of VLSI chips. Circuit activity and consequently power dissipation in CMOS circuits are highly input-pattern dependent, making the problem of maximum power estimation computationally hard. This work proposes a novel pseudo-boolean satisfiability based method that reports the exact input sequence maximizing circuit activity in combinational and sequential circuits. The method is also extended to take multiple gate transitions into account by integrating delay information into the pseudo-boolean optimization problem. An extensive suite of experiments on ISCAS85 and ISCAS89 circuits confirms the efficiency and robustness of the approach compared to simulation based techniques and encourages further research for low-power solutions using boolean satisfiability.