A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Feedback, correlation, and delay concerns in the power estimation of VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Determining accuracy bounds for simulation-based switching activity estimation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Opportunities and obstacles in low-power system-level CAD
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simulation based architectural power estimation for PLA-based controllers
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A method of redundant clocking detection and power reduction at RT level design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
A predictive system shutdown method for energy saving of event-driven computation
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Accurate power estimation for large sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Trace driven logic synthesis—application to power minimization
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
Parallel algorithms for power estimation
DAC '98 Proceedings of the 35th annual Design Automation Conference
An optimization-based error calculation for statistical power estimation of CMOS logic circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
3D CMOS SOL for high performance computing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Power invariant vector sequence compaction
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Power Design for Real-Time Systems
Real-Time Systems
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A predictive system shutdown method for energy saving of event-driven computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Function-level power estimation methodology for microprocessors
Proceedings of the 37th Annual Design Automation Conference
Analytical macromodeling for high-level power estimation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
System level online power management algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Speeding up power estimation of embedded software
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Regression-based RTL power modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance analysis of a transaction based software system with shutdown
Proceedings of the 2nd international workshop on Software and performance
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
In-place delay constrained power optimization using functional symmetries
Proceedings of the conference on Design, automation and test in Europe
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
PowerShake: a low power driven clustering and factoring methodology for Boolean expressions
Proceedings of the conference on Design, automation and test in Europe
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Petri net modeling of gate and interconnect delays for power estimation
Proceedings of the 39th annual Design Automation Conference
Power analysis techniques for SoC with improved wiring models
Proceedings of the 2002 international symposium on Low power electronics and design
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
Logic Synthesis and Verification
Power estimation of embedded systems: a hardware/software codesign approach
Readings in hardware/software co-design
Estimation of state line statistics in sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Latency effects of system level power management algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Estimating Circuit Activity in Combinational CMOS Digital Circuits
IEEE Design & Test
Instruction-level power consumption estimation of embedded processors for low-power applications
Computer Standards & Interfaces - Intelligent data acquisition and advanced computing systems
A fast and accurate delay dependent method for switching estimation of large combinational circuits
Journal of Systems Architecture: the EUROMICRO Journal
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
Ramp Up/Down Functional Unit to Reduce Step Power
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Maximization of power dissipation under random excitation for burn-in testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Process-tolerant test with energy consumption ratio
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Circuit power estimation using pattern recognition techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Low power design and its testability
ATS '95 Proceedings of the 4th Asian Test Symposium
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Monte-Carlo Approach for Power Estimation in Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC(tm) Microprocessor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Instruction Prediction for Step Power Reduction
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Leakage and leakage sensitivity computation for combinational circuits
Proceedings of the 2003 international symposium on Low power electronics and design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Early analysis tools for system-on-a-chip design
IBM Journal of Research and Development
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Efficient library characterization for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lowering power consumption in concurrent checkers via input ordering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
Pareto-optimal hardware for digital circuits using SPEA
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal - Special issue: Low-power design techniques
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
Transition-activity aware design of reduction-stages for parallel multipliers
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Power Estimation Under Uncertain Delays
Integrated Computer-Aided Engineering
Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering
An information-theoretic model for adaptive side-channel attacks
Proceedings of the 14th ACM conference on Computer and communications security
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
End-to-end validation of architectural power models
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 46th Annual Design Automation Conference
Computation of signal output probability for Boolean functions represented by OBDD
Computers & Mathematics with Applications
Proceedings of the 6th FPGAworld Conference
Integration, the VLSI Journal - Special issue: Low-power design techniques
Empirical method based on neural networks for analog power modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
A precise high-level power consumption model for embedded systems software
EURASIP Journal on Embedded Systems
Fast computation of discharge current upper bounds for clustered power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Total power modeling in FPGAs under spatial correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-dependent power estimation framework considering coupling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatically deriving information-theoretic bounds for adaptive side-channel attacks
Journal of Computer Security
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient statistical approach to estimate power considering uncertain properties of primary inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach
WSEAS Transactions on Circuits and Systems
Power estimation of CMOS circuits by neural network macromodel
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
ICATPN'06 Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency
A theoretical probabilistic simulation framework for dynamic power estimation
Proceedings of the International Conference on Computer-Aided Design
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Toward PDN resource estimation: a law of general power density
Proceedings of the System Level Interconnect Prediction Workshop
Application of internode model to global power consumption estimation in SCMOS gates
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Energy consumption in RC tree circuits with exponential inputs: an analytical model
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A method for switching activity analysis of VHDL-RTL combinatorial circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Scalable methods for analyzing the circuit failure probability due to gate oxide breakdown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
System-level power estimation tool for embedded processor based platforms
Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
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With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed.