Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Switching activity estimation using limited depth reconvergent path analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Fast Power Estimation of Large Circuits
IEEE Design & Test
A Technique for Estimating Signal Activity in Logic Circuits
Integrated Computer-Aided Engineering
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition density: a new measure of activity in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic gate-level power estimation using a novel waveform set method
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented.