Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Introduction to Probability Models, Ninth Edition
Introduction to Probability Models, Ninth Edition
A fast and accurate delay dependent method for switching estimation of large combinational circuits
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the exibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.