Low power multiplication for FIR filters
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Scheduling for power reduction in a real-time system
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Minimizing energy dissipation in high-speed multipliers
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power data processing by elimination of redundant computations
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low-power embedded SRAM macros with current-mode read/write operations
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
A low-power high-performance current-mode multiport SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications
Wireless Personal Communications: An International Journal
Exploiting Metal Layer Characteristics for Low-Power Routing
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Low-Power Design by Hazard Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low-power VLSI synthesis of DSP systems
Integration, the VLSI Journal
Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits
Analog Integrated Circuits and Signal Processing
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
LPRAM: a low power DRAM with testability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
A Technique for Estimating Signal Activity in Logic Circuits
Integrated Computer-Aided Engineering
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information Systems Frontiers
Memory reduction methodology for distributed-arithmetic- based DWT/IDWT exploiting data symmetry
IEEE Transactions on Circuits and Systems II: Express Briefs
A spurious-power suppression technique for multimedia/DSP applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
On the energy complexity of algorithms realized in CMOS, a graphics example
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
Graphics algorithms on field programmable function arrays
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
Formal verification of architectural power intent
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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