VLSI implementation of discrete wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
Area- and power-efficient design of Daubechies wavelet transforms using folded AIQ mapping
IEEE Transactions on Circuits and Systems II: Express Briefs
A pipeline VLSI architecture for high-speed computation of the 1-D discrete wavelet transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architecture for DWT/inverse DWT is proposed. It occupies 6.5-mm2 silicon area and consumes 46.8-µW power at 1 MHz for 1.2 V using 0.13-µm standard cell technology.