Ten lectures on wavelets
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
A Wavelet Tour of Signal Processing, Third Edition: The Sparse Way
Memory reduction methodology for distributed-arithmetic- based DWT/IDWT exploiting data symmetry
IEEE Transactions on Circuits and Systems II: Express Briefs
An efficient folded architecture for lifting-based discrete wavelet transform
IEEE Transactions on Circuits and Systems II: Express Briefs
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
IEEE Transactions on Signal Processing
IEEE Transactions on Consumer Electronics
A novel VLSI architecture for multidimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
VLSI Design of a Wavelet Processing Core
IEEE Transactions on Circuits and Systems for Video Technology
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In this brief, we present an efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms. The architecture is based on a two-level folded mapping technique that is developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure. The chip occupies a 2.08-mm2 silicon area, runs at 100 MHz, and consumes 4.51 mW of power in 0.18-µm CMOS technology.