A novel VLSI architecture for multidimensional discrete wavelet transform

Authors:
Qionghai Dai;Xinjian Chen;Chuang Lin
Affiliations:
Dept. of Autom., Tsinghua Univ., Beijing, China;-;-
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
2004

Citing 0
Cited 6

A Novel FPGA Architecture of a 2-D Wavelet Transform

Journal of VLSI Signal Processing Systems
Efficient array architectures for multi-dimensional lifting-based discrete wavelet transforms

Signal Processing
An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

Journal of VLSI Signal Processing Systems
Area- and power-efficient design of Daubechies wavelet transforms using folded AIQ mapping

IEEE Transactions on Circuits and Systems II: Express Briefs
A fast Discrete Wavelet Transform algorithm for visual processing applications

Signal Processing
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

Journal of Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A novel VLSI architecture for multidimensional discrete wavelet transform (mD DWT) based on a systolic array is proposed. We divide the input mD image data into 2m independent data streams, and then simultaneously pipeline them into a multi-filter chip, and finally obtain 2m samples which are from different DWT subbands per clock cycles (ccs). The proposed architecture performs a decomposition of an N1×N2×...×Nm image in about N1N2...Nm/(2m-1) ccs and requires relatively lower hardware cost than previous architectures. Besides, the advantages of the proposed architecture include very simple hardware complexity, regular data flow and low control complexity.