A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Integrated Computer-Aided Engineering
Journal of Signal Processing Systems
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Two fast architectures for the direct 2-D discrete wavelettransform
IEEE Transactions on Signal Processing
Design of an efficient VLSI architecture for 2-D discrete wavelet transforms
IEEE Transactions on Consumer Electronics
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
IEEE Transactions on Image Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
An efficient architecture for two-dimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
A novel VLSI architecture for multidimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
VLSI Design of a Wavelet Processing Core
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera's C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920驴脳驴1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.