An Efficient Architecture for a Lifted 2D Biorthogonal DWT
Journal of VLSI Signal Processing Systems
A novel VLSI architecture for multidimensional discrete wavelet transform
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Low-power and high-performance 2-D DWT and IDWT architectures based on 4-tap Daubechies filters
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Real-time 2-D wavelet transform implementation for HDTV compression
Real-Time Imaging
Folded reconfigurable architecture for VLSI wavelet filter
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
Multiplierless, reconfigurable folded architecture for VLSI wavelet filter
WSEAS Transactions on Circuits and Systems
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
Journal of Signal Processing Systems
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We propose two architectures for the direct two-dimensional (2-D) discrete wavelet transform (DWT). The first one is based on a modified recursive pyramid algorithm (MRPA) and performs a “"nonstandard” decomposition (i.e., Mallat's (1989) tree) of an N×N image in approximately 2N2/3 clock cycles (ccs). This result consistently speeds up other known architectures that commonly need approximately N2 ccs. Furthermore, the proposed architecture is simpler than others in terms of hardware complexity. Subsequently, we show how “symmetric”/“anti-symmetric” properties of linear-phase wavelet filter bases can be exploited in order to further reduce the VLSI area. This is used to design a second architecture that provides one processing unit for each level of decomposition (pipelined approach) and performs a decomposition in approximately N2/2 ccs. In many practical cases, even this architecture is simpler than general MRPA-based devices (having only one processing unit)