Ten lectures on wavelets
The Verilog Hardware Description Language, 5th Edition
The Verilog Hardware Description Language, 5th Edition
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters
PDCAT '06 Proceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies
Efficient realizations of analysis and synthesis filters based on the 2-D discrete wavelet transform
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Two fast architectures for the direct 2-D discrete wavelettransform
IEEE Transactions on Signal Processing
Reconfigurable architecture for VLSI 9/7-5/3 wavelet filter
WSEAS Transactions on Circuits and Systems
Multiplierless, reconfigurable folded architecture for VLSI wavelet filter
WSEAS Transactions on Circuits and Systems
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This paper proposes two architectures of 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first high-efficiency architecture comprises a transform module, an address sequencer, and a RAM module. The transform module has uniform and regular structure, simple control flow, and local communication. The significant advantages of the single transform module are full hardware-utilization and low-power. The second architecture features parallel and pipelined computation and high throughput. Both architectures are very suitable for VLSI implementation of new-generation image coding/decoding systems, such as JPEG-2000 and motion-JPEG. In the realization of 2-D DWT/IDWT, we focus on a VLSI implementation using 4-tap Daubechies filters, which saves power and reduces chip area.