ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A novel VLSI architecture for multidimensional discrete wavelet transform
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Low-power and high-performance 2-D DWT and IDWT architectures based on 4-tap Daubechies filters
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
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This paper presents folded architectures and scheduling algorithms for computing the 2-D DWT for analysis and synthesis filters. The folded architectures consist of two parallel computation units (one for computations along the rows and the other for computations along the columns) and two storage units to store the intermediate outputs that are generated by the two units. The scheduling algorithms range from those that try to minimise the latency to those that try to minimise the control unit complexity and keep the data flow regular. A comparison of the scheduling algorithms has been included to aid the designer in choosing an algorithm that is best suited for a particular application.