VLSI architectures of the 1-D and 2-D discrete wavelet transforms for JPEG 2000

Authors:
Sung Bum Pan;Rae-Hong Park
Affiliations:
Information Security Division, ETRI, Daejon, Korea;Department of Electronic Engineering, Sogang University, C.P.O. Box 1142, Seoul 100-611, South Korea
Venue:
Signal Processing
Year:
2002

Citing 3
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Abstract

This paper proposes efficient VLSI architectures for computation of the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transforms (DWTs) for joint photographic experts group 2000. The proposed 1-D DWT architecture computes the wavelet lowpass and highpass output sequences using the lowpass filter architecture alone, whereas the conventional architectures compute the lowpass and highpass output sequences using both lowpass and highpass filter architectures. The proposed architecture is effectively applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. The proposed architecture does not need memory and control units whereas conventional architectures need a complex control unit, memory unit, and so on. The two proposed VLSI architectures for the 2-D DWT are constructed based on block-based computation. Each M × N (N × M) block DWT is performed along the row and column directions simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively, thus the required extra processing units of the proposed architectures are much smaller than those of the conventional architectures.