A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Behavioral synthesis: digital system design using the synopsys behavioral compiler
Behavioral synthesis: digital system design using the synopsys behavioral compiler
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
An efficient VLSI architecture for 2-D wavelet image coding with novel image scan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VLSI design of 1-D DWT architecture with parallel filters
Integration, the VLSI Journal
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Design of Silicon IP Cores for Biorthogonal Wavelet Transforms
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Efficiently Searching the Optimal Design Space
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Efficient realizations of analysis and synthesis filters based on the 2-D discrete wavelet transform
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
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The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.