An efficient VLSI architecture for 2-D wavelet image coding with novel image scan

Authors:
Gauthier Lafruit;Francky Catthoor;Jan P. H. Cornelis;Hugo J. De Man
Affiliations:
IMEC, Heverlee, Belgium and Vrije Univ. Brussel, Brussels, Belgium;IMEC, Heverlee, Belgium;Vrije Univ. Brussel, Brussels, Belgium;IMEC, Heverlee, Belgium
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1999

Citing 0
Cited 7

An Integrated Systolic Array Design for Video Compression

Journal of VLSI Signal Processing Systems
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform

IEEE Transactions on Computers
Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems

Signal Processing
Low memory implementation of generic hierarchical transforms for parent-children tree (PCT) production and its application in image compression

Image Communication
An Efficient Wavelet Based Feature Extraction Method for Face Recognition

ISNN 2009 Proceedings of the 6th International Symposium on Neural Networks: Advances in Neural Networks - Part III
A robust wavelet based feature extraction method for face recognition

SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics

Quantified Score

Hi-index	0.00

Visualization

Abstract

A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line.