VLSI implementation of discrete wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
An efficient VLSI architecture for 2-D wavelet image coding with novel image scan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
Scalable wavelet coding for synthetic/natural hybrid images
IEEE Transactions on Circuits and Systems for Video Technology
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
Complexity-based program phase analysis and classification
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Wavelet-based ECG compression by bit-field preserving and running length encoding
Computer Methods and Programs in Biomedicine
IEICE - Transactions on Information and Systems
VLSI architectures for lifting based DWT: a detailed survey
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
High speed VLSI implementation of lifting based DWT
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
| Hi-index | 14.98 |
The lifting scheme has been developed as a flexible tool suitable for constructing biorthogonal wavelets recently. In this paper, we present an efficient VLSI architecture for the implementation of 1D lifting discrete wavelet transform. The architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Because of its modular, regular, and flexible structure, the design is scalable for different resolution levels. In addition, its area is independent of the length of the 1D input sequence and its latency is independent of the number of resolution levels. Since the architecture has a similar topology to a scan chain, we can modify it easily to become a testable scan-based design by adding very few hardware resources. For the computations of N-sample 1D k-level analysis (5, 3) lifting wavelet transform, the design takes N+1 clock cycles, and requires two multipliers, four adders, and (3 + 2.25 \times 2^k ) registers. In the simulation, it works with a clock period of 10 ns and achieves a processing rate of about 100\times 10^6samples/sec for k-level lifting wavelet transform.