A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform

Authors:
Jimmy C. Limqueco;Magdy A. Bayoumi
Affiliations:
The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, Louisiana 70504;The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, Louisiana 70504
Venue:
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Year:
1998

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Abstract

In this paper, an efficient semi-systolic array architecture forseparable 2-D Discrete Wavelet Transform (DWT) is introduced. Thesemi-systolic array is applicable to any convolution that requires anarbitrary subsampling function. The semi-systolic array presents a betterimplementation of the convolution function of DWT. This kind ofimplementation offers a higher efficiency compared to regular systolicimplementation when applied for 2-D DWT. The architecture has an efficiencyof at least 91% which increases proportional to the number of octaveswith no change in the architecture design except for minor modifications tothe control logic and memory size. The propose architecture is scalable fordifferent size of filter and different number of octave. The communicationrouting is minimum since data transfers are limited to immediate neighboringprocessors. The components of the architecture are fairly regular andconsist of minimum number of computational units which makes it a goodcandidate for VLSI implementation.