Logic testing and design for testability
Logic testing and design for testability
VLSI array processors
Design of an ASIP architecture for low-level visual elaborations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
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A formal methodology for the design of window generator circuits is proposed. The methodology focuses on the design of optimised dedicated structures and allows to exploit modularity for evaluating design alternatives and cost/performances trade-offs. The discussed architectural model is based on a suitable mathematical representation (called σ transformation) of a generic window generator circuit and allows both a global and a modular design style. Such features are used to design a library of universal functional blocks allowing to synthesise any type of window generator circuit. The architectural model is evaluated by implementing the functional blocks and by synthesising in VLSI technologies a set of representative window generator circuits. The trade-off between cost and performance of the synthesised window generator circuits is presented and discussed.