VLSI array processors

Authors:
S. Y. Kung
Affiliations:
Princeton Univ., Princeton, NJ
Venue:
VLSI array processors
Year:
1987

Citing 0
Cited 259

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Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

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Semi-systolic architecture for modular multiplication over GF(2m)

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A new digit-serial systolic mulitplier for high performance GF(2m) applications

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Low complexity systolic architecture for modular multiplication over GF(2m)

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Area-Time efficient systolic architecture for the DCT

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2-D discrete cosine transform (DCT) on meshes with hierarchical control modes

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Reducing the number of processors elements in systolic arrays for matrix multiplication

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CP-based SBHT-RLS algorithms for tracking channel estimates in multicarrier modulation systems

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Massively parallel systolic-array architectures for 2d IIR polyphase space–time plane-wave beam digital filters

International Journal of Circuit Theory and Applications
Synthesis of a unidirectional systolic array for matrix-vector multiplication

Mathematical and Computer Modelling: An International Journal
Scalable Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector Representation

Journal of Signal Processing Systems
Processor array design with the use of genetic algorithm

LSSC'11 Proceedings of the 8th international conference on Large-Scale Scientific Computing
Two-level pipelining of systolic array graphics engines

EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
Full-Hardware Architectures for Data-Dependent Superimposed Training Channel Estimation

Journal of Signal Processing Systems
Configurable transmitter and systolic channel estimator architectures for data-dependent superimposed training communications systems

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors

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Abstract