Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm

Authors:
Keon-Jik Lee;Kee-Won Kim;Kee-Young Yoo
Affiliations:
Department of Computer Engineering, Kyungpook National University, 1370 Sankyuk-Dong, Buk-Ku, Taegu, Republic of Korea 702-701;Department of Computer Engineering, Kyungpook National University, 1370 Sankyuk-Dong, Buk-Ku, Taegu, Republic of Korea 702-701;Department of Computer Engineering, Kyungpook National University, 1370 Sankyuk-Dong, Buk-Ku, Taegu, Republic of Korea 702-701
Venue:
Information Processing Letters
Year:
2002

Citing 6
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Abstract

This paper proposes a systematic design of a digit-serial-in-serial-out systolic multiplier for the efficient implementation of the Montgomery algorithm in an RSA cryptosystem. For processing speed, the proposed multiplier can also accommodate bit-level pipelining, thereby achieving sample speeds comparable to bit-parallel multipliers with a lower area. If the appropriate digit-size is chosen, the proposed architecture can meet the throughput requirement of a specific application with minimum hardware. The new digit-serial systolic multiplier is highly regular, nearest-neighbor connected, and thus well suited for VLSI implementation.