Hardware speedups in long integer multiplication
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Bit-level systolic arrays for modular multiplication
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
RSA cryptosystem design based on the Chinese remainder theorem
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems
Journal of VLSI Signal Processing Systems
An RNS Architecture for Quasi-Chaotic Oscillators
Journal of VLSI Signal Processing Systems
Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm
Information Processing Letters
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
Modular Arithmetic Using Low Order Redundant Bases
IEEE Transactions on Computers
An RNS Montgomery Modular Multiplication Algorithm
IEEE Transactions on Computers
Systolic multiplier for Montgomery's algorithm
Integration, the VLSI Journal
Mesh Algorithms for Multiplication and Division
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
RSA Acceleration with Field Programmable Gate Arrays
ACISP '99 Proceedings of the 4th Australasian Conference on Information Security and Privacy
Modular Exponentiation on Fine-Grained FPGA
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Montgomery in Practice: How to Do It More Efficiently in Hardware
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Data Integrity in Hardware for Modular Arithmetic
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Sliding Windows Succumbs to Big Mac Attack
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
How to fake an RSA signature by encoding modular root finding as a SAT problem
Discrete Applied Mathematics - The renesse issue on satisfiability
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 3
FPGA-Based Implementation of a Serial RSA Processor
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Hardware Algorithm for Modular Multiplication/Division
IEEE Transactions on Computers
A Novel Unified Architecture for Public-Key Cryptography
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A tamper resistant hardware accelerator for RSA cryptographic applications
Journal of Systems Architecture: the EUROMICRO Journal
A hardware version of the RSA using the Montgomery's algorithm with systolic arrays
Integration, the VLSI Journal
An 830mW, 586kbps 1024-bit RSA chip design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security
The Journal of Supercomputing
A New Systolic Architecture for Modular Division
IEEE Transactions on Computers
Fast hardware for modular exponentiation with efficient exponent pre-processing
Journal of Systems Architecture: the EUROMICRO Journal
Scalable hardware implementing high-radix Montgomery multiplication algorithm
Journal of Systems Architecture: the EUROMICRO Journal
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
An efficient CSA architecture for montgomery modular multiplication
Microprocessors & Microsystems
FPGA based communication security for wireless sensor networks
ESPOCO'05 Proceedings of the 4th WSEAS International Conference on Electronic, Signal Processing and Control
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A new modular exponentiation architecture for efficient design of RSA cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new algorithm for high-speed modular multiplication design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient fixed-size systolic arrays for the modular multiplication
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
Fault attack to the elliptic curve digital signature algorithm with multiple bit faults
Proceedings of the 4th international conference on Security of information and networks
A fast RSA implementation on itanium 2 processor
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
Bipartite modular multiplication
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
High-Speed RSA crypto-processor with radix-4 modular multiplication and chinese remainder theorem
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
| Hi-index | 15.01 |
A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.