The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Montgomery Multiplication in GF(2^k
Designs, Codes and Cryptography
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Elliptic Curve Public Key Cryptosystems
Elliptic Curve Public Key Cryptosystems
Systolic Modular Multiplication
IEEE Transactions on Computers
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A unified architecture for a public key cryptographic coprocessor
Journal of Systems Architecture: the EUROMICRO Journal
A high performance ROM-based structure for modular exponentiation
Computers and Electrical Engineering
FPGA based unified architecture for public key and private key cryptosystems
Frontiers of Computer Science: Selected Publications from Chinese Universities
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In this paper we propose a fully-parallel, bit-sliced unified architecture designed to perform modular multipication/exponentiation and GF(2^M) multiplication as the core operations of RSA and EC cryptography. The architecture uses radix-2 Montgomery technique for modular arithmetic, and a radix-4 MSD-first approach for GF(2^M) multiplication. To the best of our knowledge, it is the first unified proposal based on such a hybrid approach. The architecture structure is bit-sliced and is highly regular, modular, and scalable, as virtually any datapath length can be obtained at a linear cost in terms of hardware resources and no costs in terms of critical path. Our proposal outperforms all similar unified architectures found in the technical literature in terms of clock count and critical path. The architecture has been implemented on a Field-Programmable Gate Array (FPGA) device. A highly compact and efficient design was obtained taking advantage of the architectural characteristics.