Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
A single chip 1024 bits RSA processor
EUROCRYPT '89 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
A fast elliptic curve cryptosystem
EUROCRYPT '89 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Montgomery Multiplication in GF(2^k
Designs, Codes and Cryptography
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Cryptography: Theory and Practice,Second Edition
Cryptography: Theory and Practice,Second Edition
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Fundamentals of Computer Security
Fundamentals of Computer Security
Elliptic Curve Scalar Multiplier Design Using FPGAs
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Dual-Field Arithmetic Unit for GF(p) and GF(2m)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Design and Implementation of a Coprocessor for Cryptography Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
A Novel Unified Architecture for Public-Key Cryptography
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Fast VLSI arithmetic algorithms for high-security elliptic curve cryptographic applications
IEEE Transactions on Consumer Electronics
IEEE Transactions on Consumer Electronics
An implementation of elliptic curve cryptosystems over F2155
IEEE Journal on Selected Areas in Communications
An efficient implementation of montgomery powering ladder in reconfigurable hardware
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
FPGA based unified architecture for public key and private key cryptosystems
Frontiers of Computer Science: Selected Publications from Chinese Universities
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This paper presents a unified architecture for public key cryptosystems that can support the operations of the Rivest-Shamir-Adleman cryptogram (RSA) and the elliptic curve cryptogram (ECC). A hardware solution is proposed for operations over finite fields GF(p) and GF(2^p). The proposed architecture presents a unified arithmetic unit which provides the functions of dual-field modular multiplication, dual-field modular addition/subtraction, and dual-field modular inversion. A new adder based on the signed-digit (SD) number representation is provided for carry-propagated and carry-less operations. The critical path of the proposed design is reduced compared with previous full adder implementation methods. Experimental results show that the proposed design can achieve a clock speed of 1GHz using 776K gates in a 0.09@mm CMOS standard cell technology, or 150MHz using 5227 CLBs in a Xilinx Virtex 4 FPGA. While the different technologies, platforms and standards make a definitive comparison difficult, based on the performance of our proposed design, we achieve a performance improvement of between 30% and 250% when compared with existing designs.