Mathematica: a system for doing mathematics by computer (2nd ed.)
Mathematica: a system for doing mathematics by computer (2nd ed.)
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
The design space layer: supporting early design space exploration for core-based designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
A hardware version of the RSA using the Montgomery's algorithm with systolic arrays
Integration, the VLSI Journal
Enhanced montgomery multiplication on DSP architectures for embedded public-key cryptosystems
EURASIP Journal on Embedded Systems - Embedded System Design in Intelligent Industrial Automation
A unified architecture for a public key cryptographic coprocessor
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA), use, as basic operation, the modular exponentation. This ASIC works as a coprocessor with a special set of instructions specialized on dealing with high accuracy integers, as well as on the rapid evaluation of modular multiplications and exponentations. The algorithm, the hardware architecture, the design methodology and the results are described in detail.