Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Cryptography and network security (2nd ed.): principles and practice
Cryptography and network security (2nd ed.): principles and practice
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
IEEE Transactions on Computers
Comparison of Three Modular Reduction Functions
CRYPTO '93 Proceedings of the 13th Annual International Cryptology Conference on Advances in Cryptology
Implementing 1,024-Bit RSA Exponentiation on a 32-Bit Processor Core
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Design and Implementation of a Coprocessor for Cryptography Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Enhanced montgomery multiplication on DSP architectures for embedded public-key cryptosystems
EURASIP Journal on Embedded Systems - Embedded System Design in Intelligent Industrial Automation
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Rivest-Shamir-Adleman (RSA) is one of the most widely preferred algorithms used in public-key cryptography systems. RSA has a very slow ciphering rate if used in software. The use of a specific hardware is the only reasonable solution in applications where performance is the key factor. To speed up the modular multiplication and squaring, bit level systolic arrays are used with the Montgomery's modular multiplication algorithm to constitute the core of modular exponentiation operation. The squaring systolic structure is also performed in parallel with the systolic multiplication in the modular exponentiation. The novel idea in this paper is to use the systolic array cells with increased performance of up to 20% and use them in a single row organization. The final RSA design is configurable and can operate both for encryption and decryption. 1024-bit RSA algorithm is designed for the Xilinx Virtex FPGA and 0.7 µ ASIC.