Minimal Weight Digit Set Conversions
IEEE Transactions on Computers
A hardware version of the RSA using the Montgomery's algorithm with systolic arrays
Integration, the VLSI Journal
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Analysis and design of a hardware/software trusted platform module for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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This paper describes how long-wordlength (1024-bit) modular exponentiation may be implemented on a standard 32-bit microprocessor core with a total execution time of under 1 second. The design does not use a long-wordlength arithmetic co-processor. Instead, all arithmetic operations are reduced to 32-bit additions, subtractions and binary shifts, and the processor is augmented with a small hardware enhancement to significantly accelerate accumulation of shifted multi-precision numbers. Target performance is achieved by trading fast arithmetic hardware for extra RAM, to facilitate pre-computation of digit multiples and powers. Signed sliding window algorithms are introduced for exponentiation, multiplication and reduction operations, and attention is paid to the integration of enhanced security features such as blinding and verification.