Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Floating point arithmetic teaching for computational science
Future Generation Computer Systems - Special issue: Selected papers from the workshop on education in computational sciences held at the ICCS 2002
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
Multiple constant multiplication by time-multiplexed mapping of addition chains
Proceedings of the 41st annual Design Automation Conference
Functional pearl: implicit configurations--or, type classes reflect the values of types
Haskell '04 Proceedings of the 2004 ACM SIGPLAN workshop on Haskell
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Proceedings of the 42nd annual Design Automation Conference
Power optimization for universal hash function data path using divide-and-concatenate technique
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Custom-optimized multiplierless implementations of DSP algorithms
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Embedded floating-point units in FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
Journal of VLSI Signal Processing Systems
Gradual and tapered overflow and underflow: a functional differential equation and its approximation
Applied Numerical Mathematics - The third international conference on the numerical solutions of volterra and delay equations, May 2004, Tempe, AZ
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers
IEEE Transactions on Computers
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy-efficient acceleration of MPEG-4 compression tools
EURASIP Journal on Embedded Systems
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
An FPGA-based face detector using neural network and a scalable floating point unit
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay efficient 32-bit carry-skip adder
VLSI Design
Fast exponentiation based on common-multiplicand-multiplication and minimal-signed-digit techniques
International Journal of Computer Mathematics
Real-time differentiation of the multi-dimensional sampled functions
SIP'08 Proceedings of the 7th WSEAS International Conference on Signal Processing
A unified architecture for a public key cryptographic coprocessor
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Information Sciences: an International Journal
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Arithmetic Circuit Verification Based on Symbolic Computer Algebra
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design Methods of Radix Converters Using Arithmetic Decompositions
IEICE - Transactions on Information and Systems
International Journal of Reconfigurable Computing
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Gradual and tapered overflow and underflow: A functional differential equation and its approximation
Applied Numerical Mathematics
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Area-efficient nonrestoring radix-2k division
Digital Signal Processing
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
A high throughput FFT processor with no multipliers
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Conventional adders with fine grained redundancy injection
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Formalization of a parameterized parallel adder within the coq theorem prover
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploration of heterogeneous FPGAs for mapping linear projection designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards logic functions as the device
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
A novel linear array for discrete cosine transform
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
A novel linear array for discrete cosine transform
WSEAS Transactions on Circuits and Systems
Formal analysis of end-around-carry adder in floating-point unit
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Journal of Systems Architecture: the EUROMICRO Journal
ICONIP'06 Proceedings of the 13th international conference on Neural information processing - Volume Part III
The effect of multi-bit correlation on the design of field-programmable gate array routing resources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Spin wave functions nanofabric update
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Fault attack to the elliptic curve digital signature algorithm with multiple bit faults
Proceedings of the 4th international conference on Security of information and networks
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
An efficient hardware architecture for a neural network activation function generator
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
Analog Integrated Circuits and Signal Processing
Formal proof for a general architecture of hybrid prefix/carry-select adders
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
An effective educational module for Booth's multiplication algorithm
Journal of Computing Sciences in Colleges
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Modular arithmetic and fast algorithm designed for modern computer security applications
ACIIDS'12 Proceedings of the 4th Asian conference on Intelligent Information and Database Systems - Volume Part III
Mathematical and Computer Modelling: An International Journal
Design of a high precision logarithmic converter in a binary floating point divider
Concurrency and Computation: Practice & Experience
Design of a fault-tolerant conditional sum adder
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power Wallace multiplier design based on wide counters
International Journal of Circuit Theory and Applications
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Multispeculative additive trees in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Energy recovery and logical reversibility in adiabatic CMOS multiplier
RC'13 Proceedings of the 5th international conference on Reversible Computation
Hardware reuse in modern application-specific processors and accelerators
Microprocessors & Microsystems
Ultra-low-power adder stage design for exascale floating point units
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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