Variants of an Improved Carry Look-Ahead Adder
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Journal of the ACM (JACM)
A fast hybrid carry-lookahead/carry-select adder design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
IEEE Transactions on Computers
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Reconfigurable hardware solution to parallel prefix computation
The Journal of Supercomputing
Timing-power optimization for mixed-radix ling adders by integer linear programming
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
A 485ps 64-bit parallel adder in 0.18µm CMOS
Journal of Computer Science and Technology
FleXilicon architecture and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
Implementation of recursive ling adders in CMOS VLSI
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line adaptive parallel prefix computation
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Circuit design style for energy efficiency: LSDL and compound domino
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A class of almost-optimal size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
| Hi-index | 14.98 |
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of implementation compared to the parallel-prefix structures proposed for the traditional definition of carry lookahead equations and reduces the fanout requirements of the design. Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.