Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
Multi-voltage low power convolvers using the polynomial residue number system
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Mesh Algorithms for Multiplication and Division
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Compiling SA-C Programs to FPGAs: Performance Results
ICVS '01 Proceedings of the Second International Workshop on Computer Vision Systems
Timing for Associative Operations on the MASC Model
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Logarithmic Number System for Low-Power Arithmetic
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512
ISC '02 Proceedings of the 5th International Conference on Information Security
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Wave steering to integrate logic and physical syntheses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
IEEE Transactions on Computers
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System
IEEE Transactions on Computers
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation
Proceedings of the 1st conference on Computing frontiers
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Functional pearl: implicit configurations--or, type classes reflect the values of types
Haskell '04 Proceedings of the 2004 ACM SIGPLAN workshop on Haskell
Adding Limited Reconfigurability to Superscalar Processors
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
Addition Related Arithmetic Operations via Controlled Transport of Charge
IEEE Transactions on Computers
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IEEE Transactions on Computers
IEEE-Compliant IDCT on FPGA-Augmented TriMedia
Journal of VLSI Signal Processing Systems
High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
High-level synthesis for large bit-width multipliers on FPGAs: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automating custom-precision function evaluation for embedded processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Energy Scalable Universal Hashing
IEEE Transactions on Computers
A Carry-Free Architecture for Montgomery Inversion
IEEE Transactions on Computers
IEEE-compliant IDCT on FPGA-augmented TriMedia
Journal of VLSI Signal Processing Systems
Constructing zero-deficiency parallel prefix adder of minimum depth
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
A digit serial algorithm for the integer power operation
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Implementing quantum genetic algorithms: a solution based on Grover's algorithm
Proceedings of the 3rd conference on Computing frontiers
Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution
IEEE Transactions on Computers
Optimizing high speed arithmetic circuits using three-term extraction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of VLSI Signal Processing Systems
Modulo p = 3 Checking for a Carry Select Adder
Journal of Electronic Testing: Theory and Applications
Integration, the VLSI Journal - Special issue: Low-power design techniques
Real-Time Systems
ByZFAD: a low switching activity architecture for shift-and-add multipliers
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Truncated Online Arithmetic with Applications to Communication Systems
IEEE Transactions on Computers
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
Integration, the VLSI Journal
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
A unified evaluation framework for coarse grained reconfigurable array architectures
Proceedings of the 4th international conference on Computing frontiers
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
Enhancing FPGA performance for arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
Prototyping neuroadaptive smart antenna for 3G wireless communications
EURASIP Journal on Applied Signal Processing
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
A new high dynamic range moduli set with efficient reverse converter
Computers & Mathematics with Applications
Efficient synthesis of compressor trees on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Reconfigurable solutions for very-long arithmetic with applications in cryptography
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
Analog Integrated Circuits and Signal Processing
Efficient implementation of constant coefficient division under quantization constraints
ICC'05 Proceedings of the 9th International Conference on Circuits
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Delay efficient 32-bit carry-skip adder
VLSI Design
A Hardware Acceleration Platform for Digital Holographic Imaging
Journal of Signal Processing Systems
A BCD-based architecture for fast coordinate rotation
Journal of Systems Architecture: the EUROMICRO Journal
Towards fault tolerant parallel prefix adders in nanoelectronic systems
Proceedings of the conference on Design, automation and test in Europe
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
An efficient architecture for designing reverse converters based on a general three-moduli set
Journal of Systems Architecture: the EUROMICRO Journal
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A support vector machine with integer parameters
Neurocomputing
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Arithmetic Circuit Verification Based on Symbolic Computer Algebra
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Journal of Signal Processing Systems
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
CMOS Implementation of Generalized Threshold Functions
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A dynamic ADC test processor for built-in-self-test of ADCs
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor
Microelectronics Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Extended sequential logic for synchronous circuit optimization and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new redundant binary booth encoding for fast 2n-bit multiplier design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Exploiting inherent parallelisms for accelerating linear Hough transform
IEEE Transactions on Image Processing
High-performance special function unit for programmable 3-D graphics processors
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
A new symbolic substitution based addition algorithm
Computers & Mathematics with Applications
IEEE Communications Magazine
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers
Journal of Signal Processing Systems
An architecture of a high-speed digital hologram generator based on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Area-efficient nonrestoring radix-2k division
Digital Signal Processing
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Integration, the VLSI Journal - Special issue: Low-power design techniques
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A comparative study of different FFT architectures for software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Toward acceleration of RSA using 3D graphics hardware
Cryptography and Coding'07 Proceedings of the 11th IMA international conference on Cryptography and coding
Multiplier-less and table-less linear approximation for square and square-root
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Performance: complexity comparison of receivers for a LTE MIMO-OFDM system
IEEE Transactions on Signal Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Exploiting finite precision information to guide data-flow mapping
Proceedings of the 47th Design Automation Conference
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
Parallel merged multiplier-accumulator coprocessor optimized for digital filters
Computers and Electrical Engineering
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
Truncated binary multipliers with variable correction and minimum mean square error
IEEE Transactions on Circuits and Systems Part I: Regular Papers
High-speed FPGA 10's complement adders-subtractors
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Lightweight cryptography and RFID: tackling the hidden overheads
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Automatic code generation on a MOVE processor using Cartesian genetic programming
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Design and analysis of matching circuit architectures for a closest match lookup
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Proposed low power, high speed adder-based 65-nm Square root circuit
Microelectronics Journal
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shift-adds design of digit-serial multiple constant multiplications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoding the golden code: a VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Robust finite field arithmetic for fault-tolerant public-key cryptography
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Nature inspiration for support vector machines
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part II
Low-Power aspects of nonlinear signal processing
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Public key cryptography in sensor networks—revisited
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
A new construction adder based on Chinese abacus algorithm
Computers and Electrical Engineering
Arithmetic data value speculation
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Public key cryptography and RFID tags
CT-RSA'07 Proceedings of the 7th Cryptographers' track at the RSA conference on Topics in Cryptology
Reduced redundant arithmetic applied on low power multiply-accumulate units
EHAC'12/ISPRA/NANOTECHNOLOGY'12 Proceedings of the 11th WSEAS international conference on Electronics, Hardware, Wireless and Optical Communications, and proceedings of the 11th WSEAS international conference on Signal Processing, Robotics and Automation, and proceedings of the 4th WSEAS international conference on Nanotechnology
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
On carry-save strategies for multiply-accumulate arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
Mathematical model of stored logic based computation
Mathematical and Computer Modelling: An International Journal
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dependability evaluation of time-redundancy techniques in integer multipliers
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Correlation power analysis attack of AES on FPGA using customized communication protocol
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Faster pairing coprocessor architecture
Pairing'12 Proceedings of the 5th international conference on Pairing-Based Cryptography
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
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