Goodness-of-fit techniques
Parallel Random Number Generation for VLSI Systems Using Cellular Automata
IEEE Transactions on Computers
A fast normal random number generator
ACM Transactions on Mathematical Software (TOMS)
Testing random number generators
WSC '92 Proceedings of the 24th conference on Winter simulation
Inversive pseudorandom number generators: concepts, results and links
WSC '95 Proceedings of the 27th conference on Winter simulation
Fast pseudorandom generators for normal and exponential variates
ACM Transactions on Mathematical Software (TOMS)
Maximally equidistributed combined Tausworthe generators
Mathematics of Computation
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Good random number generators are (not so) easy to find
Selected papers from the 2nd IMACS symposium on Mathematical modelling---2nd MATHMOD
Noise generators for the simulation of digital communication systems
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Tables of maximally equidistributed combined LFSR generators
Mathematics of Computation
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
A Comparison of Methods for Generating Normal Deviates on Digital Computers
Journal of the ACM (JACM)
Automatic sampling with the ratio-of-uniforms method
ACM Transactions on Mathematical Software (TOMS)
Normal Random Numbers: Using Machine Analysis to Choose the Best Algorithm
ACM Transactions on Mathematical Software (TOMS)
A simple method for generating gamma variables
ACM Transactions on Mathematical Software (TOMS)
A new class of linear feedback shift register generators
Proceedings of the 32nd conference on Winter simulation
Introduction to Wireless Systems
Introduction to Wireless Systems
Design of High Speed AWGN Communication Channel Emulator
Analog Integrated Circuits and Signal Processing
Combined generators with components from different families
Mathematics and Computers in Simulation - Special issue: 3rd IMACS seminar on Monte Carlo methods - MCM 2001
Continuous random variate generation by fast numerical inversion
ACM Transactions on Modeling and Computer Simulation (TOMACS)
An embedded true random number generator for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A Versatile High Speed Bit Error Rate Testing Scheme
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
On the complexity of curve fitting algorithms
Journal of Complexity
A Gaussian Noise Generator for Hardware-Based Simulations
IEEE Transactions on Computers
IEEE Transactions on Computers
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis
IEEE Transactions on Computers
A hardware gaussian noise generator using the wallace method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA-based accelerator for the verification of leading-edge wireless systems
Proceedings of the 46th Annual Design Automation Conference
A compact 1.1-Gb/s encoder and a memory-based 600-Mb/s decoder for LDPC convolutional codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
A single FPGA filter-based multipath fading emulator
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
Hardware implementation of Nakagami and Weibull variate generators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hard-ware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to ± 15 times the standard deviation σ) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of ±6.66σ. To accurately achieve a range of ±9.4σ, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.