Digital communications: fundamentals and applications
Digital communications: fundamentals and applications
Accelerating Bit Error Rate Testing Using a System Level Design Tool
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware implementation of Nakagami and Weibull variate generators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The design of communication systems becomes increasingly challenging as product complexity and cost pressures increase and as the time-to-market is shortened more than ever before. This paper presents a bit error rate tester (BERT) for the hardware-based verification of the physical layer (PHY) layer of emerging wireless systems. We integrate fundamental modules of a typical PHY layer along with the channel simulator onto a single field-programmable gate array (FPGA). For a proof-of-concept, we present the results of a FPGA-based performance verification exercise for a multiple antenna system. The proposed BERT system significantly decreases the test time compared to conventional software-based verification, hence increasing designer productivity.